زيادةview
AN7166 explains how Ripple Injection in ACOT (Adaptive Constant-On-Time) control shapes control-loop gain, poles/zeros, bandwidth, phase margin, and transient performance using frequency-domain (S-domain) impedance modeling. It also contrasts a detailed frequency-domain design approach with a simplified ripple-based method and emphasizes bench validation.
Key Design Parameters and Example Values (from Source)
| المعلمة | Meaning (as stated) | Example value(s) shown |
|---|---|---|
| RINJ | Ripple injection resistor (part of ZB) | 200 kΩ (detailed example: CINJ=15 nF, CFF=560 pF); 16.2 kΩ (MIC28515 load transient exampلو) |
| CINJ | DC blocking capacitor for ripple injection (part of ZB) | 15 nF (detailed example); 0.1 µF (MIC28515 transient exampلو) |
| سي اف اف | Feed-forward capacitor (part of ZF) | 560 pF (detailed example); 560 pF/CFF=4.7 nF (simplified approach example); 4.7 nF (MIC28515 transient exampلو) |
| VFB | Feedback ripple amplitude used/targeted for comparator operation | 150 mV (after recalculation in one design step); 100 mV (simplified approach target); 220 mV (MIC28515 example calculated vs test) |
| FC (crossover frequency) | Loop crossover frequency where gain crosses 0 dB | ~24.8 kHz (measured vs targeted); ~25 kHz (simplified approach example statement) |
| هامش الطور | Stability margin from Bode measurement | ~68° (measured in one example); >80° (simplified approach statement) |
| Z1 / first zero placement | Zero primarily set by RINJ and CINJ; placed about 1–2 decades below FLC in example | In one example: first zero placed two decades below FLC |
| اف ال سي | LC resonant frequency used for placing CINJ (first zero) | 5 kHz (detailed exampلو) |
| Transient response metrics (one exampلو) | Undershoot, recovery, settling | Undershoot ~120 mV; recovery within ~13.4 µs; settling ~30 µs (noted in source text; recovery/settling timing given) |
| Transient load step (one exampلو) | Load step used for evaluation | 2.5 A to 5 A with fast transition time |
Quick Start: Ripple Injection Loop Design and Validation
- Work from the ACOT Type 3 ripple injection approach, where ripple is derived from the switching node through an RC ripple network (RINJ, CINJ) and shaped with a feed-forward capacitor (CFF).
- Use the frequency-domain relationships to understand how the ratio of the injection impedance to the feed-forward impedance (ZB/ZF) affects loop gain (and thus bandwidth and stability).
- Design pole/zero placement using the ripple injection and feed-forward components: Z1 is mainly set by RINJ and CINJ; Z2 is mainly set by R1 and CFF.
- Select ripple injection components (for example, CINJ and CFF) and then calculate/recalculate the resulting feedback ripple VFB; verify VFB is within the device’s recommended operating range.
- Estimate or target the desired crossover frequency FC via the loop gain profile and confirm through frequency-domain (Bode) measurement.
- Perform bench validation in the time domain: measure feedback ripple at the comparator node and evaluate load transient response (undershoot, recovery, settling) and switching behavior.
إرشادات استكشاف الأخطاء وإصلاحها
- Irregular switching or instability after changing RINJ: increasing RINJ increases the impedance ratio ZB/ZF and reduces VFB, which can improve transient response; however, reducing VFB too much can make the FB comparator sensitive to noise, jitter, and layout parasitics, potentially causing irregular switching or instability. Adjust RINJ and confirm sufficient VFB via the device data sheet and bench testing.
- Unexpected comparator behavior during dynamic conditions: Verify that feedback ripple at the feedback node remains well-defined during transients; this indicates proper ripple injection and stable comparator operation.
- Mismatch between predicted and measured crossover frequency/phase margin: Treat Bode analysis as guidance only—layout effects, component tolerances, and parasitics can shift real behavior. Re-check component values and validate stability using bench measurements (Bode plus load transient response).
التعليمات
- What is the main role of the Type 3 ripple injection network in ACOT loop design?
- It shapes the control-loop gain through the ripple injection impedance (ZB) and the feed-forward impedance (ZF), directly influencing bandwidth, phase margin, and transient behavior.
- How are Z1 and Z2 zeros primarily determined in the ACOT loop model?
- Z1 is mainly set by RINJ and CINJ, while Z2 is mainly set by R1 and CFF; these zeros help compensate for phase lag introduced by the output LC double pole.
- Why is bench testing required even after frequency-domain loop design?
- Real implementations are affected by parasitics, component tolerances, and layout non-idealities not fully captured in analysis. Bench testing is necessary to confirm crossover frequency, phase margin, and transient performance.
- What trade-off is highlighted when increasing RINJ?
- increasing RINJ improves transient response by increasing ZB/ZF and reducing VFB, but reducing VFB too much can increase comparator sensitivity to noise, jitter, and layout parasitics, potentially causing irregular switching or instability.
- Does the analysis explicitly consider the output capacitor ESR zero?
- No. It is not explicitly considered because Type 3 ripple injection is typically used with very low-ESR output capacitors (e.g., MLCCs), where the ESR zero is often at very high frequency beyond the control-loop region of interest.
المستندات / الموارد
 | AN7166 Control-Loop Analysis and Performance Optimization |
مراجع
- microchip.commicrochip.com
- microchip.com/en-us/about/legal-information/microchip-trademarkswww.microchip.com
- microchip.com/en-us/product/MIC28515www.microchip.com
- microchip.com/en-us/support/design-help/client-support-serviceswww.microchip.com
- دليل المستخدمmanual.tools
Published: August 7, 2026