شعار MICROCHIP

Polar Fire FPGA Splash Kit JESD204B Standalone Interface
ملاحظة الطلب
AN5978

محتويات يخفي
1 مقدمة
2 متطلبات التصميم
3 المتطلبات الأساسية
4 تصميم تجريبي
5 هيكل تسجيل الوقت
6 إعادة تعيين الهيكل
7 Simulating the Polar Fire® JESD204B Design
8 إعداد العرض التوضيحي
9 Programming the Device Using Flash Pro Express
10 تشغيل العرض التوضيحي
11 Appendix A: References
12 Appendix B: Running the TCL Script
13 سجل المراجعة
14 دعم Microchip FPGA
15 معلومات الرقاقة
16 المستندات / الموارد
16.1 مراجع

مقدمة

(اطرح سؤالا)

This document describes how to run the JESD204B standalone demo design on the Polar Fire ® Splash Board using the JESD204B Standalone Demo GUI application. The GUI application is packaged along with the design files. The demo design is a reference design built using the Polar Fire high-speed transceiver blocks and the CoreJESD204BTX and CoreJESD204BRX IP cores. It operates in Loopback mode by sending the CoreJESD204BTX data to the CoreJESD204BRX IP core through the transceiver lanes, which are looped back on the board. This loopback setup facilitates a standalone JESD interface demo that does not require Analog-to-Digital Converter (ADC) or Digital-to-Analog Converters (DAC).
Microchip Polar Fire devices have embedded, high-speed transceiver blocks that can handle data rates ranging from 250 Mbps to 12.5 Gbps. The transceiver (PF_XCVR) module integrates several functional blocks to support multiple high-speed serial protocols within the FPGA. JESD204B is a high-speed serial interface standard for data converters developed by the JEDEC committee. The JESD204B standard reduces the number of data inputs and outputs between the high-speed data converters and receivers.
Microchip provides CoreJESD204BTX and CoreJESD204BRX IP cores that implement the transmitter and receiver interfaces of the JESD204B standard. These IP cores are easy to integrate with JESD204B- based data converters to develop high-bandwidth applications such as wireless infrastructure transceivers, software-defined radios, medical imaging systems, and radar and secure communications. These IP cores support link widths from x1 to x4, and link rates from 250 Mbps to 12.5 Gbps per lane using subclass 0, 1 and 2.
For more information about the JESD204B interface design implementation, and all the necessary blocks and IP cores instantiated in Libero® SoC, see Demo Design.

The JESD204B standalone interface design can be programmed using any of the following options:

  • Using the .job file:لبرمجة الجهاز باستخدام .job file مع التصميم files, see Programming the Device Using Flash Pro Express.
  • Using Libero SoC: To program the device using Libero SoC, see Running the Demo Design. Use this option when the demo design is modified

متطلبات التصميم

(اطرح سؤالا)

The following table lists the resources required to run the demo.
الجدول 1-1. متطلبات التصميم

متطلبات إصدار
نظام التشغيل Windows®  10 and 11
الأجهزة
Polar Fire® Splash Kit with MPF300T-1FCG484E device Rev 2 or later
برمجة For all the software versions needed to create this reference design, see readme.txt file المقدمة في التصميم files.
فلاش برو اكسبريس
GUI executable (provided with the design files)
نظام ليبرو® على رقاقة

المتطلبات الأساسية

(طرح سؤال)

قبل البدء، قم بتنفيذ الخطوات التالية:

  • Download and install Libero® SoC (as indicated in the website for this design) on the host PC from Libero SoC Documentation.
  • قم بتنزيل التصميم التجريبي fileس من www.microchip.com/en-us/application-notes/an5978.
  • Install the GUI application by running the setup.exe file متوفر في التصميم files folder: <$Design_Files_Directory>/mpf_an5978_df/GUI
    At the end of the installation, you may be prompted to download and install the FPGA_GUI_Pack, if it is not already available on your system.
  • Alternatively, you can manually download and install the Microchip FPGA_GUI_Pack.

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Symbol 1 هام: أ Libero® Gold license is required to evaluate your designs using the Polar Fire® Splash Kit.

تصميم تجريبي

(طرح سؤال)

The Polar Fire® JESD204B demo design is developed to interface JESD204B-compliant data converters with Polar Fire devices. The design functions as follows:

  1. The DATA_HANDLE_0 block interfaces with the GUI. The GUI enables the selection of either PRBS or waveform input.
  2. The DATA_HANDLE_0 block forwards the input selection to the DATA_GENERATOR_0 block, which generates and sends the corresponding input data to the CoreJESD204BTX IP core.
  3. The CoreJESD204BTX IP core performs JESD204B transmitter functions based on the configuration and transmits the data to the PF_XCVR (transceiver) IP core.
  4. The encoded data is received by the CoreJESD204BRX IP core because the TX and RX lanes of the PF_XCVR block are looped back.
  5. The CoreJESD204BRX IP core performs JESD204B receiver functions based on the configuration and transmits the data to the GUI for viewing the selected input.

المهم: متى a data error or link error is selected on the GUI, the error generator block generates that error and displays it on the GUI.
The following figure shows the hardware implementation of the JESD204B interface demo.

Figure 3-1. Hardware Implementation Block Diagram

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Block Diagram

3.1. Design Implementation (طرح سؤال)
The following figure shows the Libero® design implementation of the JESD204B interface demo.

Figure 3-2. JESD204B Interface Design

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Interface Design

The following table lists the important input and output signals of the design.
الجدول 3-1. إشارات الإدخال والإخراج

إشارة وصف
إشارات الإدخال
LANE0_RXD_P and LANE0_RXD_N Transceiver receiver differential inputs
ارست_ن External reset obtained from push button switch on board
RX Receiver of UART interface
REF_CLK_PAD_P_0 and
مرجع_CLK_PAD_N_0		 Differential reference clock obtained from the on-board 125 MHz oscillator
SEL_IN[3:0] Signal mapped to DIPs 1, 2, 3 and 4 of SW8 dip slide switch used to debug the
status and errors
إشارات الإخراج
LANE0_TXD_P and LANE0_TXD_N Transceiver transmitter differential outputs
LED_OUT[7:0] Signal that indicates whether link is up or down
TX Transmitter of UART interface

3.2. تكوين IP (طرح سؤال)
The hardware design for the JESD204B interface includes the following blocks.
3.2.1. Data Handle (طرح سؤال)
The data handle (DATA_HANDLE_0) block receives the input data selection and link or data error generation information from the GUI. This block also sends the data output received from the CoreJESD204BRX core and the data or link status error to the GUI for viewعمل.
3.2.2. Data Generator (طرح سؤال)
The data generator has a PRBS generator and a waveform generator. The PRBS generator generates PRBS7, PRBS15, PRBS23 and PRBS31 patterns. An error insertion mode implemented in the PRBS generator inserts an error into the PRBS sequence. The waveform generator generates sine, sawtooth, triangle and square waveforms. The data generator feeds a 64-bit test pattern to the JESD204BTX core, which subsequently transmits the data to the transceiver.
3.2.3. PF_TPSRAM (طرح سؤال)
There are two instances of PF_TPSRAM blocks, the PF_TPSRAM_C0 block stores the JESD204B link status before sending it to the GUI. The PF_TPSRAM_C1 block stores the data received from the CoreJESD204BRX before sending the data to the GUI.
3.2.4. Error Generator (طرح سؤال)
The error generator block (ERR_GEN_0) generates link errors by sending random data between CoreJESD204BTX and PF_XCVR when link error generation is selected in the GUI.
3.2.5. PRBS_checker (طرح سؤال)
The data checker receives 64-bit data from the CoreJESD204BRX IP core and checks whether the received data is correct. It generates an error count and a status signal, which are transmitted to the GUI for status indication. The data checker exclusively checks the PRBS sequences generated by the data generator.
3.2.6. LED Debug (طرح سؤال)
The LED debug block (LED_DEBUG_BLK_0) debugs the JESD204B link status and other errors. When the link is up, LEDs 1, 2, 3, 4, 5 and 6 glow, while LEDs 7 and 8 do not glow (with DIP 1, 2, 3 and 4 are set to low on the SW8 dip slide switch).
3.2.7. Init_monitor (طرح سؤال)
When the DEVICE_INIT_DONE signal from Init_monitor block goes high, the transceiver is completely configured. This signal is and ed with ARST_N signal to get proper reset signal for the design.
3.2.8. CORERESET_PF (طرح سؤال)
CoreReset_PF synchronizes resets to the user-specified clock domain. This ensures that while the assertion is asynchronous, the negation is synchronous with the clock.
3.2.9. CoreJESD204BTX (طرح سؤال)
CoreJESD204BTX is the transmitter interface of the JEDEC JESD204B standard. For this demo design, this IP core is configured in Libero®, as shown in the following figure.

Figure 3-3. CoreJESD204BTX Configurator

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Configurator

For more information about CoreJESD204BTX, see CoreJESD204BTX Handbook.
3.2.10. CoreJESD204BRX (Ask a Question)
CoreJESD204BRX is the receiver interface of the JEDEC JESD204B standard. For this demo design, this IP core is configured in Libero®, as shown in the following figure.
Note: To view the complete configuration, open the configurator of IP from within the design.

Figure 3-4. CoreJESD204BRX Configurator

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Configurator 2

For more information about CoreJESD204BRX, see CoreJESD204BRX Handbook.
3.2.11. Transceiver Interface (طرح سؤال)
The Polar Fire ® high-speed transceiver (PF_XCVR) is a hard IP block designed to support high-speed data rates ranging from 250 Mbps to 12.5 Gbps. In this demo, the transceiver block (PF_XCVR) is configured in 8b10b mode with a Clock Data Recovery (CDR) reference clock of 125 MHz to support 5.0 Gbps data rate.
The Polar Fire transmit PLL (PF_TX_PLL) provides the reference clock feed to the transceiver. The dedicated reference clock (PF_XCVR_REF_CLK) drives the PF_TX_PLL to generate the desired output clock for the 5.0 Gbps data rate.
يوضح الشكل التالي تكوين واجهة جهاز الإرسال والاستقبال.
Note: To view the complete configuration, open the configurator of IP from within the design.

Figure 3-5. Transceiver Interface Configurator

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Configurator 3

هيكل تسجيل الوقت

(طرح سؤال)

In the reference design, there are three clock domains:

  • RX_CLK (125 MHz)
  • TX_CLK (125 MHz)
  • FAB_REF_CLK (125 MHz)

The on-board 125-MHz crystal oscillator drives the XCVR reference clock, which provides clock to the DATA_GENERATOR, CoreJESD204BTX, ERR_GEN, CoreJESD204BRX, LED_DEBUG, PRBS_CHECKER, TPSRAM C0 & C1 and DATA_HANDLE.
MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Symbol 1 هام: إذا there is a change in the data rate or reference clock of the transceiver, you must reconfigure COREUART.
ويوضح الشكل التالي بنية تسجيل الوقت.
الشكل 4-1. بنية التوقيت

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Clocking Structure

إعادة تعيين الهيكل

(طرح سؤال)

The DEVICE_INIT_DONE and external reset signal ARST_N are mapped to pin N4 on the Splash Kit.
These signals initiate the system reset (FABRIC_RESET_N) through the res_syn_0 block.
The FABRIC_RESET_N signal from the res_syn_0 block provides a direct reset to the following modules:

  • CoreJESD204BRX
  • CoreJESD204BTX
  • PF_XCVR (LANE0_PMA_ARST_N)

Additionally, FABRIC_RESET_N is connected to the reset synchronizer block, which distributes synchronized reset signals to the following functional blocks:

  • prbs_checker
  • DATA_HANDLE
  • DATA_GENERATOR
  • ERR_GEN
  • LED_DEBUG_BLK
    RX_RESET_N output from the CoreJESD204BRX module supplies reset signals to:
  • LANE0_PCS_ARST_N input of the PF_XCVR_0 module
  • LED_DEBUG block (EPCS_0_RX_RESET_N)

ويوضح الشكل التالي هيكل إعادة الضبط.
الشكل 5-1. إعادة ضبط الهيكل

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Reset Structure

Simulating the Polar Fire® JESD204B Design

(طرح سؤال)
لمحاكاة التصميم، قم بالخطوات التالية:

  1. Start Libero®, and select Project > Tool Profileس….
  2. In the Tool Profiles window, select Synthesis and Simulation on the Tools panes and select the latest active installation directory paths for these two tools.

For Simulation, browse the design files folder, create Libero Project using provided TCL scripts, and click Simulate as highlighted in the Figure 6-2. For more information, see Appendix B: Running the TCL Script.
A testbench is provided to simulate the JESD204B PRBS pattern and waveform selection. The following figure shows the interaction between testbench and the design.
Figure 6-1. Testbench and JESD204B Demo Design Interaction

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Design Interaction

The testbench generates the test selection for the PRBS input (PRBS7, PRBS15, PRBS23 and PRBS31) and waveform input (sine wave, sawtooth wave, triangle wave and square wave). It also monitors the JESD204B output status signals (SYNC_N, ALIGNED and CGS_ERR) for the verification of JESD204B phases, and PRBS checker output status signals O_BAD and O_ERROR[4:0].
To simulate the design, in the Design Flow tab, double-click Simulate under Verify Pre Synthesized Design. The Simulate option is highlighted in the following figure.

Figure 6-2. Simulating the Design

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Simulating the Design

When the simulation is initiated, simulation tool compiles all the design source files, runs the simulation, and configures the waveform viewer to show the simulation signals.
Note: In certain cases, a prompt may appear asking for the selection of an active stimulus before starting the simulation. To resolve this, navigate to the Stimulus Hierarchy, right-click PF_JESD204B_SA_TOP_TB_8b (top.v) and select Set as Active Stimulus, as shown in the following figure.
Figure 6-3. Set As Active Stimulus

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Active Stimulus

6.1. Simulation Flow (Ask a Question)
The following steps describe the JESD204B testbench simulation flow:

  1. At the start, the NSYSRESET signal resets all of the components.
  2. After the transceiver block is initialized, the TB_RX_READY signal is asserted high.
  3. The JESD204BRX issues a synchronization request by driving the TB_SYNC_N pin low.
  4. The JESD204BRX block checks the k28.5 characters transmitted by the JESD204BTX block.
  5. The CGS and ILA phase starts after the TB_SYNC_N signal is asserted high.
  6. The testbench checks whether the CGS_ERR signal asserts low or not, and completes the code group synchronization phase.
  7. The JESD204BRX link asserts the TB_SYNC_N signal to high.
  8. After the successful completion of the CGS phase, the JESD204BTX block starts the Initial Lane
    Alignment (ILA) sequence by transmitting four multi-frames in the following sequence:
    – First frame at TB_TX_SOMF = 0x8
    – Second frame at TB_TX_SOMF = 0x2
    – Third frame at TB_TX_SOMF = 0x8
    – Fourth frame at TB_TX_SOMF = 0x2
  9. The JESD204BRX link starts receiving four multi-frames in the following sequence:
    – First frame at TB_TX_SOMF = 0x8
    – Second frame at TB_TX_SOMF = 0x2
    – Third frame at TB_TX_SOMF = 0x8
    – Fourth frame at TB_TX_SOMF = 0x2
  10. The ILA phase test passes if all JESD204BRX DATA_OUT is properly received with frame alignment.
  11. After successful completion of the ILA phase, the JESD204BTX block enters into the data phase.
  12. In the data phase, the following data is fed to the JESD204BTX block: PRBS7, PRBS15, PRBS23 and PRBS31 using the PRBS generator.
  13. Sine, Square, Saw and triangular waves are generated from the waveform generator.
  14. The PRBS checker checks the received PRBS pattern against the expected PRBS pattern.
  15. The waveform output can be viewed in the simulation window on corresponding wave selection as shown in Figure 6-5.
  16. If the data checker does not detect any error, the testbench issues a TESTBENCH PASSED message stating that the simulation was successful. If an error is detected, the testbench issues a TESTBENCH FAILED message to indicate that the testbench has failed.
    While the simulation is running, you can see the status of the test cases in the Transcript window of Model Sim, as shown in the following figure.

Figure 6-4. Transcript Window

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Transcript Window

After simulation, the Waveform window displays the simulation waveforms as shown in the following figure.
Note: You may notice some warnings in the log. These appear because UART is not used in the simulation. The simulation is focused only on JESD, while UART and RAM are included for GUI purposes.
Figure 6-5. Simulation Waveform Window

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Waveform Window

إعداد العرض التوضيحي

(طرح سؤال)

After generating the bitstream, the Polar Fire® device must be programmed. To program the Polar Fire device, perform the following steps:

  1. Ensure that the jumper settings on the board are same as listed in the following table.
    الجدول 7-1. إعدادات العبور
    سترة وصف  تقصير
    ج11 Close pin 1 and 2 for programming through the FTDI chip.
    Open pin 1 and 2 for programming through an external FlashPro4 or FlashPro5 device.    		 يفتح
    J3 Jumper to select the core voltage.
    Close pin 1 and 2 for 1.05 V.
    Open pin 1 and 2 for 1.0 V.    		 مغلق
    ج10 Close pin 1 and 2 for programming through the external SPI flash.
    If J10 is open, it allows SPI slave programming using the FTDI chip.    		 يفتح
  2. قم بتوصيل كابل إمداد الطاقة بموصل J2 على اللوحة.
  3. Connect the USB cable from the host PC to the J1 (FTDI port) on the board.
  4. Power On the board using the SW1 slide switch.
    When the board is powered up, power supply LEDs 1 to 4 glow. For more information about LEDs on the Polar Fire Splash Board, see UG0786: Polar Fire FPGA Splash Kit User Guide.
  5. In Libero Design Flow tab, double-click Run PROGRAM Action.

ل view السجل المقابل file, navigate to Reports tab, right-click Run Program Action and select View تقرير.
When the device is successfully programmed, a green tick mark appears as shown in the following figure. For information about how to run the JESD204B standalone demo, see Running the Demo.

Figure 7-1. Device Programming Completed

MICROCHIP AN5978 Polar Fire FPGA Splash Kit - Device Programming

Programming the Device Using Flash Pro Express

(طرح سؤال)
This section describes how to program the Polar Fire® device with the programming job file using Flash Pro Express. The .job file متوفر في التصميم التالي files folder location: mpf_an5978_df/Programming_Files/top. job.

لبرمجة الجهاز ، قم بتنفيذ الخطوات التالية:

  1. على الكمبيوتر المضيف ، قم بتشغيل برنامج Flash Pro Express.
  2. To create a new project, click New or New Job Project from Flash Pro Express Job from Project menu.
  3. أدخل ما يلي في مربع الحوار New Job Project من Flash Pro Express Job:
    - وظيفة برمجة file: انقر فوق "استعراض" وانتقل إلى الموقع الذي توجد به الوظيفة file يقع وحدد ملف file. The default location is: mpf_an5978_df/Programming_Files/top. job.
    – Flash Pro Express job project location: Click Browse and navigate to the Flash Pro Express project location.
    Figure 8-1. New Job Project from Flash Pro Express JobMICROCHIP AN5978 Polar Fire FPGA Splash Kit - New Job Project
  4. انقر فوق موافق. البرمجة المطلوبة file تم تحديده وجاهزًا للبرمجة في الجهاز.
  5. The Flash Pro Express window appears, as shown in the following figure. Confirm that a programmer number appears in the Programmer field. If not, confirm the board connections and click Refresh/Rescan Programmers.
    الشكل 8-2. برمجة الجهازMICROCHIP AN5978 Polar Fire FPGA Splash Kit - Programming the Device
  6. انقر فوق تشغيل. عند برمجة الجهاز بنجاح ، يتم عرض حالة RUN PASSED كما هو موضح في الشكل التالي.
    الشكل 8-3. FlashPro Express—تم تشغيله بنجاحMICROCHIP AN5978 Polar Fire FPGA Splash Kit - FlashPro Express
  7. أغلق Flash Pro Express أو انقر فوق "خروج" في علامة التبويب "المشروع".

تشغيل العرض التوضيحي

(طرح سؤال)

This section describes how to use the JESD204B GUI to run the JESD204B demo on the Polar Fire® Splash Board.
9.1. Installing the GUI (طرح سؤال)
To run the demo, install the JESD204B GUI. The GUI allows selection of different PRBS test patterns as input, and displays the JESD204B status signals and the PRBS status received from the board.
The Waveform tab of the GUI displays the output waveforms received from the board for each waveform selected as input.

لتثبيت واجهة المستخدم الرسومية، قم بالخطوات التالية:

  1. Install the JESD204B_GUI application (setup.exe) from the following design files folder: mpf_an5978_df/GUI.
  2. To start the GUI application, double-click the JESD204B_GUI application from the installation directory.

9.2. Running the Demo Design (طرح سؤال)
To run the JESD204B demo, perform the following steps:

  1. Connect the jumpers and set up the Polar Fire® Splash Board as described in steps 1 to 4 of Setting Up the Demo.
  2. In Device Manager on the host PC, note the COM port associated with the USB serial converter
    C. To determine the COM port, check the Location field in the properties of each COM port.
  3. On the Start menu of the host PC, click JESD204B_GUI.
  4. From the list of COM ports, select the COM port identified in the step 2, and click Connect, as shown in the following figure.
    Figure 9-1. COM Port SelectionMICROCHIP AN5978 Polar Fire FPGA Splash Kit - COM Port SelectionMICROCHIP AN5978 Polar Fire FPGA Splash Kit - Symbol 1 Important: Port numbers may vary. In this example, COM port 32 is the correct port to select.
    After successful connection, the Host Connection indicator turns green, as shown in the following figure.
    Figure 9-2. Successful Host ConnectionMICROCHIP AN5978 Polar Fire FPGA Splash Kit - Successful Host ConnectionThe following table lists the status signals displayed in the JESD204B GUI.
    Table 9-1. Status Signals in JESD204B GUI
    إشارة وصف
    اتصال المضيف Shows the UART communication status.
    حالة الرابط Shows the communication link status between TX and RX.
    SYNC_N Indicates the JESD204B status.
    محاذاة Indicates that all transceiver lanes are aligned.
    RX VALID Indicates that RX data is valid. In 8b10b mode, indicates that comma alignment has occurred and the CDR is locked.
    PRBS Status Indicates PRBS error.
    عدد الأخطاء Provides the number of errors that occurred during PRBS check
    CGS_ERR Indicates a code group synchronization error.
    NIT_ERR Indicates a “not in table” error.
    DISP ERR Indicates a disparity error.
    LINK_CD_ERR Indicates a link configuration data mismatch.
    UCC_ERR Indicates an “unexpected control character” error.
  5. From the Input Selection list, select the pattern to be transmitted, and click START, as shown in the following figure.
    Figure 9-3. Pattern SelectionMICROCHIP AN5978 Polar Fire FPGA Splash Kit - Pattern SelectionThe selected pattern is sent over the serial transmit link and received by CoreJESD204BRX, which checks for errors. At any time, the JESD204B status can be monitored using the status signals on the GUI, as shown in the following figure.
    Figure 9-4. Link Status and JESD204B StatusMICROCHIP AN5978 Polar Fire FPGA Splash Kit - Link Status
  6. To generate an error in the PRBS data, click Generate Data Error.
    The PRBS Status indicator turns red, and the Error Count field displays the number of errors, as shown in the following figure.
    Figure 9-5. Data ErrorMICROCHIP AN5978 Polar Fire FPGA Splash Kit - Data Error
  7. Click Clear Error to clear the errors in the PRBS data and reset the PRBS status.
    The PRBS Status indicator turns green, and the Error Count changes to 0, as shown in the following figure.
    Figure 9-6. Data Error ClearedMICROCHIP AN5978 Polar Fire FPGA Splash Kit - Data Error Cleared
  8. To generate a link error between CoreJESD204BTX and the transceiver lane, click Generate Link Error.
    The Link Status, SYNC_N, ALIGNED, RX VALID, DISP_ERR and CGS_ERROR indicators turn red, as shown in the following figure.
    Figure 9-7. Link ErrorMICROCHIP AN5978 Polar Fire FPGA Splash Kit - Link Error
  9. To clear the link error, click Clear Error.
    The status indicators turn green, as shown in the following figure.
    Figure 9-8. Clear Link ErrorMICROCHIP AN5978 Polar Fire FPGA Splash Kit - Clear Link Error
  10. To change the pattern, select Triangle from the Input Selection list.
    The selected pattern is sent over the serial transmit link and received by CoreJESD204BRX. At any time, the JESD204B status can be monitored using the status signals on the GUI.
  11. ل view the waveform received from CoreJESD204BRX, click the Waveform tab, as shown in the following figure.
    Figure 9-9. Triangle WaveformMICROCHIP AN5978 Polar Fire FPGA Splash Kit - Triangle Waveform
  12. To end the demo, click Stop and close the GUI.

Appendix A: References

(طرح سؤال)

This section lists documents that provide more information about the JESD204B standard and IP cores used in the demo design.

Appendix B: Running the TCL Script

(طرح سؤال)

يتم توفير نصوص TCL في التصميم fileمجلد s ضمن الدليل HW. إذا لزم الأمر، يمكن إعادة إنتاج تدفق التصميم من تنفيذ التصميم حتى إنشاء الوظيفة file. To run the TCL, perform the following steps:

  1. قم بتشغيل برنامج Libero®.
  2. حدد مشروع> تنفيذ البرنامج النصي….
  3. انقر فوق "استعراض" وحدد script.tcl من دليل الأجهزة الذي تم تنزيله.
  4. انقر فوق تشغيل.

After successful execution of TCL script, Libero project is created within HW directory. For more information about TCL scripts, see mpf_an5978_df/HW/TCL_Script_readme.txt.
For more details on TCL commands, see TCL Commands Reference Guide. For any queries encountered when running the TCL script, contact Technical Support.

سجل المراجعة

(طرح سؤال)

يصف محفوظات المراجعة التغييرات التي تم تنفيذها في المستند. يتم سرد التغييرات حسب المراجعة ، بدءًا من المنشور الحالي.

المراجعة  تاريخ  وصف
A 08/2025 The following is the list of changes made in the revision A of the document:
• The document was migrated to the Microchip template.
• The document number was updated from 50200796 to DS00005978.
• The document ID was updated from DG0796 to AN5978.
3.0 — This document is updated with respect to Libero® SoC Polar Fire v2.2 release.
2.0 — This document is updated with respect to Libero SoC Polar Fire v2.1 release.
1.0 — أول نشر لهذه الوثيقة.

دعم Microchip FPGA

تدعم مجموعة منتجات Microchip FPGA منتجاتها بخدمات دعم متنوعة ، بما في ذلك خدمة العملاء ، ومركز الدعم الفني للعملاء ، أ webالموقع، ومكاتب المبيعات في جميع أنحاء العالم.
يُقترح على العملاء زيارة موارد Microchip عبر الإنترنت قبل الاتصال بالدعم لأنه من المحتمل جدًا أن تكون استفساراتهم قد تم الرد عليها بالفعل.
اتصل بمركز الدعم الفني من خلال webعلى الموقع www.microchip.com/support. اذكر رقم جزء جهاز FPGA ، وحدد فئة الحالة المناسبة ، وقم بتحميل التصميم fileأثناء إنشاء حالة دعم فني.
اتصل بخدمة العملاء للحصول على دعم غير تقني للمنتجات ، مثل تسعير المنتج وترقيات المنتج ومعلومات التحديث وحالة الطلب والتفويض.

  • من أمريكا الشمالية، اتصل على 800.262.1060
  • من بقية العالم، اتصل على 650.318.4460
  • فاكس من أي مكان في العالم 650.318.8044

معلومات الرقاقة

العلامات التجارية
اسم وشعار "Microchip" وشعار "M" والأسماء والشعارات والعلامات التجارية الأخرى هي علامات تجارية مسجلة وغير مسجلة لشركة Microchip Technology Incorporated أو الشركات التابعة لها و/أو الشركات الفرعية في الولايات المتحدة و/أو دول أخرى ("علامات Microchip التجارية"). يمكن العثور على معلومات حول العلامات التجارية لشركة Microchip على https://www.microchip.com/en-us/about/legalinformation/microchip-trademarks.
ISBN: 979-8-3371-1709-6

إشعار قانوني
لا يجوز استخدام هذا المنشور والمعلومات الواردة فيه إلا مع منتجات Microchip ، بما في ذلك تصميم واختبار ودمج منتجات Microchip مع تطبيقك. استخدام هذه المعلومات بأي طريقة أخرى ينتهك هذه الشروط. يتم توفير المعلومات المتعلقة بتطبيقات الجهاز فقط لراحتك وقد تحل محلها التحديثات. تقع على عاتقك مسؤولية التأكد من أن التطبيق الخاص بك يلبي المواصفات الخاصة بك. اتصل بمكتب مبيعات Microchip المحلي للحصول على دعم إضافي أو احصل على دعم إضافي على www.microchip.com/en-us/support/design-help/client-support-services.

يتم توفير هذه المعلومات من قبل شركة MICROCHIP "كما هي". لا تقدم شركة MICROCHIP أي تعهدات أو ضمانات من أي نوع سواء كانت صريحة أو ضمنية، مكتوبة أو شفوية، قانونية أو غير ذلك، فيما يتعلق بالمعلومات بما في ذلك على سبيل المثال لا الحصر أي ضمانات ضمنية بعدم الانتهاك وقابلية التسويق والملاءمة لغرض معين، أو الضمانات المتعلقة بحالتها أو جودتها أو أدائها.
لن تكون شركة مايكرو شيب مسؤولة بأي حال من الأحوال عن أي خسارة أو ضرر أو تكلفة أو نفقات غير مباشرة أو خاصة أو عقابية أو عرضية أو تبعية من أي نوع كانت مرتبطة بالمعلومات أو استخدامها، مهما كان سببها، حتى لو تم إخطار مايكرو شيب بإمكانية حدوث ذلك أو كانت الأضرار متوقعة. إلى أقصى حد يسمح به القانون، لن تتجاوز مسؤولية مايكرو شيب الإجمالية عن جميع المطالبات بأي شكل من الأشكال المتعلقة بالمعلومات أو استخدامها مبلغ الرسوم، إن وجدت، التي دفعتها مباشرة لشركة مايكرو شيب مقابل المعلومات.
إن استخدام أجهزة Microchip في تطبيقات دعم الحياة و/أو السلامة يكون على مسؤولية المشتري بالكامل، ويوافق المشتري على الدفاع عن Microchip وتعويضها وحمايتها من أي أضرار أو مطالبات أو دعاوى أو نفقات ناجمة عن مثل هذا الاستخدام. لا يتم نقل أي تراخيص، ضمناً أو بطريقة أخرى، بموجب أي حقوق ملكية فكرية لشركة Microchip ما لم يُنص على خلاف ذلك.

ميزة حماية رمز أجهزة Microchip
لاحظ التفاصيل التالية لميزة حماية الكود على منتجات Microchip:

  • تتوافق منتجات Microchip مع المواصفات الواردة في ورقة بيانات Microchip الخاصة بها.
  • تعتقد شركة مايكروشيب أن مجموعة منتجاتها آمنة عند استخدامها بالطريقة المقصودة، وضمن مواصفات التشغيل، وفي ظل الظروف العادية.
  • تقدر شركة Microchip حقوق الملكية الفكرية الخاصة بها وتحميها بقوة. إن محاولات انتهاك ميزات حماية الكود الخاصة بمنتجات Microchip محظورة تمامًا وقد تنتهك قانون الألفية الجديدة لحقوق طبع ونشر المواد الرقمية.
  • لا تستطيع شركة Microchip ولا أي شركة أخرى مصنعة لأشباه الموصلات ضمان أمان التعليمات البرمجية الخاصة بها. حماية الكود لا تعني أننا نضمن أن المنتج "غير قابل للكسر".
    ورمز الحماية في تطور مستمر. تلتزم شركة Microchip بالتحسين المستمر لميزات حماية التعليمات البرمجية لمنتجاتنا.

شعار MICROCHIP ملاحظة الطلب
© 2025 Microchip Technology Inc. والشركات التابعة لها
DS00005978A –

المستندات / الموارد

MICROCHIP AN5978 Polar Fire FPGA Splash Kit [بي دي اف] دليل المستخدم
AN5978 Polar Fire FPGA Splash Kit, AN5978, Polar Fire FPGA Splash Kit, Fire FPGA Splash Kit, FPGA Splash Kit, Splash Kit

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